搜索资源列表
DDS
- DDS正弦波发生模块 基于verilog语言实现 在cycloneii系列FPGA上经过验证 频率步进1khz 共有256个点-The DDS sine wave module based on verilog language achieve in cycloneii series FPGA proven frequency stepping 1khz 256 points
FPGA-DDS-algorithm
- 采用FPGA的DDS算法Verilog程序的实现-FPGA DDS algorithm Verilog program implementation
DDS
- 直接数字频率合成器dds,用verilog实现,经过quartus验证-Direct digital frequency synthesizer the dds, used verilog achieved after quartus verify
dds
- verilog编写的dds发生器,修改频率字可改频率-dds in verilog
DDS
- 用verilog语言实现,DDS信号发生与嵌入式逻辑分析仪的调用,程序功能完整 -Using verilog language, DDS signal generator with embedded logic analyzer called, the program features a complete
DDS_dac9764
- verilog语言编写的DDS信号源,采用DAC9764-verilog DDS signal source language, using DAC9764
DDS
- FPGA产生DDS,未使用IP核,内含VERILOG程序-FPGA generates DDS, unused IP core, containing VERILOG program
DDS_Ad9854_Verilog
- DDS控制模块 AD9854 VERILOG-DDS control module AD9854 VERILOG
dds_compiler_v4_0
- Verilog的DDS实现正弦波输出。这个模块是不可综合的,但是已经综合了,-Verilog DDS
DDS_TLC5620
- DDS函数信号发生器 tlc5620 verilog-dds tlc5620 verilog
dds
- 采用硬件描述语言verilog进行DDS变换的实现的代码-Using hardware descr iption languages Verilog implementation of DDS converter code
DDS
- 用Verilog HDL 编写的一个最基本的DDS程序,发生正弦波-Verilog HDL prepared with a basic DDS program, the occurrence of a sine wave
DDS
- Verilog HDL实现FPGA的DDS功能,含有实验原理与代码程序-FPGA Verilog HDL realize the DDS function, principles and codes containing experimental procedures
DDS
- 基于fpga的正余弦波形发生器,Verilog代码,测试通过。-Cosine waveform generator fpga based, Verilog code, the test passes.
DDS-MY-WORK-1
- FPGA模拟数字信号发生器DDS verilog-FPGA analog and digital signal generator DDS verilog
DDS
- 基于fpga的DDS详细设计方案 verilog语言 正弦计算器则对该相位值计算数字化正弦波幅度(芯片一般通过查表得到)。DDS芯片输出的一般是数字化的正弦波,因此还需经过高速D/A转换器和低通滤波器才能得到一个可用的模拟频率信号。-Direct Digital Synthesizer base on fpga use verilog Sine calculator to calculate the value of the digital phase sine wave amplitu
DDS
- verilog编写,使用fpga中dds手法,可以输出任意波形的发生信号。-verilog write, use the dds fpga way, you can output an arbitrary waveform signal occurs.
dds
- 在quartus软件上,采用verilog实现DDS功能。- using verilog realize DDS function On quartus software.
dds
- 这是本人在学校做的一个DDS信号发生器,频率相位可调。输入时钟50Mhz-DDS phase frequency adjustable Verilog
DDS
- Verilog实现DDS线性调频,Verilog实现DDS线性调频-Verilog implementation of DDS linear FM,Verilog implementation of DDS linear FM